wafer-scale engine
In plain wordsA single giant processor made from nearly a whole dinner-plate-sized silicon wafer instead of the small chips normally cut from it, so data rarely has to leave the chip.
A processor that occupies most of a 300 mm silicon wafer — a square of about 46,000 mm², roughly 56 times the area of the largest GPU die — instead of being diced into separate chips; in particular, Cerebras Systems' Wafer Scale Engine (WSE) line. Keeping hundreds of thousands of cores, their SRAMSRAM, abbr.: The fastest kind of computer memory, built directly into processor chips. It is quick but takes up a lot of space, so chips hold only a little of it. and the network joining them on one piece of silicon yields enormous on-chip memory bandwidth and avoids slow off-chip links, which suits low-latency inferenceinference, n.: Drawing a conclusion from evidence. In today's AI it most often means running an already-trained model to get an answer, as opposed to training it. and fine-grained parallel work. Manufacturing defects, unavoidable at this size, are tolerated by building in spare cores and routing around faulty ones. The WSE-3 (March 2024, 5 nm process) has 4 trillion transistors, 900,000 cores and 44 GB of on-chip SRAM; models too large for that memory must stream weights from external memory or be split across systems.
Origin
Wafer-scale integration was attempted in the 1970s and 1980s, most famously by Gene Amdahl's Trilogy Systems (founded 1980), but foundered on manufacturing yield. Cerebras, founded in 2015 by Andrew Feldman and four colleagues, revived it with the WSE-1, presented in August 2019 with 1.2 trillion transistors and 400,000 cores.
Usage note
Tesla's Dojo pursued a related approach, joining 25 separate dies on a wafer-sized carrier rather than building a single wafer-sized die.
Related
- AI acceleratorAI accelerator, n.: Any chip built or tuned to speed up AI — graphics chips, Google's TPUs, phone 'neural engines' and many startup designs. Such chips do the heavy math of training and running models.
- SRAMSRAM, abbr.: The fastest kind of computer memory, built directly into processor chips. It is quick but takes up a lot of space, so chips hold only a little of it.
- chipletchiplet, n.: One of several smaller chips that are made separately and then joined inside a single package to work as one processor, which is cheaper than making one giant chip and lets makers reuse parts.
- advanced packagingadvanced packaging, n.: Ways of joining several chips very closely inside one package — side by side on a silicon base or stacked on top of each other — so they act almost like one bigger chip.
- memory wallmemory wall, n.: The growing gap between how fast chips can calculate and how fast they can fetch data from memory. Processors increasingly sit idle, waiting for numbers to arrive.
- chipletchiplet, n.: One of several smaller chips that are made separately and then joined inside a single package to work as one processor, which is cheaper than making one giant chip and lets makers reuse parts.
Mentioned in
AI acceleratorAI accelerator, n.: Any chip built or tuned to speed up AI — graphics chips, Google's TPUs, phone 'neural engines' and many startup designs. Such chips do the heavy math of training and running models., CerebrasCerebras, prop. n.: An American chip company that makes a single giant processor the size of a whole silicon wafer, used to train and run AI models very quickly., chipletchiplet, n.: One of several smaller chips that are made separately and then joined inside a single package to work as one processor, which is cheaper than making one giant chip and lets makers reuse parts., memory wallmemory wall, n.: The growing gap between how fast chips can calculate and how fast they can fetch data from memory. Processors increasingly sit idle, waiting for numbers to arrive., SRAMSRAM, abbr.: The fastest kind of computer memory, built directly into processor chips. It is quick but takes up a lot of space, so chips hold only a little of it.